As one of scaling techniques for increasing the density of integrated circuit devices, a multi-gate transistor has been proposed, in which a fin- or nanowire-shaped multi-channel active pattern (or silicon body) is formed on a substrate and a gate formed on a surface of the multi-channel active pattern.
Since the multi-gate transistor uses a three-dimensional (3D) channel, scaling of the multi-gate transistor is easily achieved. In addition, current controlling capability can be improved even without increasing a gate length of the multi-gate transistor. Further, a short channel effect (SCE), in which an electric potential of a channel region is affected by a drain voltage, can be effectively suppressed.